Introduction

In the MIPS architecture, an exception is a general label for interrupts and errors that require the processor to temporarily abandon sequential execution. An interrupt is an asynchronous request from an external device (e.g., timer, network), while a trap is a synchronous request from software (e.g., a system call). Errors detected inside the CPU (e.g., illegal instructions, misaligned accesses) are also treated as exceptions. When an exception occurs, the CPU saves the current program counter (PC) and status in dedicated registers, enters kernel mode, and jumps to an exception handler.

Overview of MIPS Exception Types

MIPS processors generate exceptions for a variety of reasons, including:

  • Reset & Non‑Maskable Interrupt (NMI)
  • Hardware errors (bus/cache errors)
  • External interrupts
  • Address errors (misaligned or illegal addresses)
  • Reserved instruction
  • TLB exceptions (misses, modification)
  • System calls
  • Breakpoints
  • Trap instructions
  • Integer overflow
  • Floating‑point exceptions
  • Timers / Watchpoints

Major Exceptions and Their Meanings

ExcCodeName (Mnemonic)Meaning / Typical Cause
0Interrupt (Int)A hardware interrupt line is active; jumps to the general or interrupt vector depending on configuration.
1TLB modification (Mod)Write via a TLB entry whose Dirty bit is clear; software must update the TLB or treat as protection violation.
2TLBLTLB miss (load or instruction fetch) — no valid TLB entry for the referenced virtual address.
3TLBSTLB miss on store — no valid TLB entry for the referenced virtual address during a store.
4AdELAddress error on load/execute — misaligned access or user access to a kernel‑only address.
5AdESAddress error on store — misaligned store or illegal address on store.
6IBEInstruction bus error — error fetching an instruction (invalid physical memory or unimplemented region).
7DBEData bus error — error during data access on the physical bus.
8SyscallExecuted SYSCALL; used by user programs to request OS services.
9Breakpoint (Bp)Executed BREAK; typically used by debuggers.
10Reserved instruction (RI)Attempted to execute an undefined/unimplemented opcode or higher‑order ISA/ASE operation.
11Coprocessor unusable (CpU)Coprocessor instruction executed while the corresponding Status.CU bit was 0 (disabled).
12Overflow (Ov)Fixed‑point arithmetic overflow (e.g., add/sub result doesn’t fit in two’s complement).
13Trap (Tr)Trap instruction (TEQ, TNE, TGE, TLT, etc.) evaluated true.
14VCEIVirtual coherency exception on instruction fetch; implementation‑dependent cache/parity issue.
15FPEFloating‑point exception signaled by the FPU (invalid, overflow, underflow, divide‑by‑zero, etc.).
16C2ECoprocessor 2 exception (implementation‑defined).
23WatchWatchpoint (debug) on an address match; may be deferred if Status.EXL or Status.ERL set.
31VCEDVirtual coherency exception on data; implementation‑specific.

NOTE: In addition to the above, Reset and NMI force the processor into a special error level indicated by Status.ERL.

Detailed Causes

1) TLB‑Related Exceptions

  • Mod: Write to a page whose TLB entry is marked read‑only (Dirty bit clear).
  • TLBL/TLBS: No valid TLB entry for the address on load/fetch or store. The failing virtual address is saved to BadVAddr; a masked form goes to Context to assist lookups.

2) Address Errors and Bus Errors

  • AdEL/AdES: Misaligned access or illegal user access to kernel space. Hardware stores the offending address in BadVAddr and jumps to the handler.
  • IBE/DBE: Errors reported by the physical memory system (e.g., parity/ECC, unimplemented region). These are not MMU faults and typically do not set BadVAddr.

3) System Calls, Breakpoints, and Traps

  • Syscall: Deliberately triggers kernel entry to request services.
  • Breakpoint (Bp): Raised by BREAK; used for debugging.
  • Trap (Tr): Trap instructions encode conditions; an exception is raised when the condition is true (useful for assertions/run‑time checks).

4) Reserved Instruction and Coprocessor Exceptions

  • RI: Attempt to execute an opcode/function marked reserved, higher‑order ISA/ASE, or an unimplemented coprocessor opcode.
  • CpU: Executing coprocessor instructions when the coprocessor is disabled (Status.CU[z] == 0); the handler may enable the unit or emulate the operation.

5) Arithmetic, Floating‑Point, and Watch Exceptions

  • Ov: Fixed‑point arithmetic overflow is reported (no silent wraparound).
  • FPE: FPU signals FP exceptions; sub‑codes available via the FCSR; exceptions are precise and the faulting PC is in EPC.
  • Watch: Access to a watched address triggers a debug exception (address/mask stored in WatchHi/WatchLo). When EXL/ERL are set, the exception can be deferred and indicated via Cause.WP.

How the MIPS CPU Handles Exceptions

  1. Save the PC. The faulting (or next) instruction address is written to EPC. If the fault occurred in a branch delay slot, Cause.BD is set and EPC points to the branch.
  2. Record the cause. Cause.ExcCode indicates the, exception; for coprocessors, Cause.CE identifies which unit; for interrupts, bitfields reflect active lines. For MMU faults, BadVAddr (and masked Context) capture the address.
  3. Switch to kernel mode; disable interrupts. Status shifts (KU/IE stacks) so the CPU enters kernel mode with interrupts disabled, supporting nested exceptions.
  4. Select an exception vector. Fixed addresses are used for entry (e.g., reset, UTLB refill, general exceptions). The exact vector depends on type and the Status.BEV (boot) and Cause.IV bits and may reside in kseg0 during normal operation.
  5. Jump to the handler & save context. The handler saves general‑purpose registers (often via k0/k1) and dispatches based on Cause.
  6. Service the exception. Examples: refill or install TLB entries; adjust protections or kill the process; deliver signals for arithmetic/FP exceptions; enable / allocate coprocessor state; handle external interrupts; or initialize/diagnose on reset/NMI/cache errors (with ERL and ErrorEPC usage where applicable).
  7. Return. Restore registers and execute ERET (or RFE on MIPS‑I) to resume from EPC (or ErrorEPC if ERL set). Status bits are shifted right to restore prior privilege/interrupt state.

Precise vs. Imprecise Exceptions

MIPS aims for precise exceptions: all prior instructions complete and no subsequent instruction modifies architectural state when the exception is taken. However, with non‑blocking caches and out‑of‑order memory systems, some errors (e.g., late bus/cache errors) may be imprecise, in which case EPC may not identify the exact faulting instruction and software may need to abort or restart.

Conclusion

MIPS uses a unified exception mechanism to handle events such as system calls, TLB misses, misaligned accesses, illegal instructions, and device interrupts. The Cause register encodes the reason, EPC records where to resume, and the CPU enters kernel mode and jumps to a fixed vector. The OS then services the condition (e.g., refilling a TLB, delivering a signal, servicing an interrupt) and returns with ERET to resume normal execution.